1. Field of the Invention
The present invention relates to a conductive wiring in a semiconductor device and a method of manufacturing the wiring, and more particularly to a wiring and method of manufacturing a wiring in a semiconductor device in which a bridge generation between neighboring conductive patterns caused by a scratch formed during a CMP process is prevented.
2. Description of the Related Art
In the manufacture of integrated circuits, planarization processes for various semiconductor materials are required to remove defects such as crystal defects, crookedness, scratches and roughness. Recently, there has been much progress in planarization processes along with the advancements of semiconductor devices, and chemical mechanical polishing (CMP) is widely utilized to improve a planarization degree among other planarization methods such as a reflowing method, an etch back method and the like. Particularly, since the planarization degree of an underlying layer affects the stability of a multi-layered wiring process, the CMP process attracts much attention as an advantageous approach for improving the quality and reliability of semiconductor devices.
The CMP process is commonly implemented for insulation layers. Then, an applying material on the insulation layer is deposited on a planarized layer. The planarized surface provides a constant depth of focus during photolithography exposure such that a surface provide,; a constant depth of focus during photolithography exposure such that a photoresist pattern wit a good profile can be produced.
The CMP process is implemented while fixing a thin and flat wafer. A layer such as an insulation layer or a metal layer is polished with pressure using a slurry having alumina or silica composition as a polishing agent. During the polishing process, it is difficult to prevent the generation of micro-scratches. The size, depth or number of the micro-scratches depends on the viscosity or state of the slurry. Some scratches might induce a fatal defect in semiconductor devices. The size of the scratches varies from several tens of angstroms to several thousand angstroms. Typically, scratches of several hundred to several thousand angstroms in size cannot be completely removed after the subsequent deposition of a conductive material. Such a scratch can cause formation of a bridge between conductive patterns.
At the region having a sub-micron design rule, the pitch of the conductive pattern is very small, and accordingly, insulating space between conductive patterns become small. Thus, a possibility of inducing a connection between neighboring conductive patterns and an undesirable short between them is increased when the scratch formed on the insulation space is filled with the conductive material.
When the CMP process is applied to the planarization of an insulation layer and wiring, a damascene process is commonly utilized for the formation of a metal pattern and a metal plug process is applied for filling a contact hole. The damascene process is implemented by forming an insulation layer, then depositing metal and planarizing by utilizing the CMP process. Conventionally, the metal pattern is formed by blanket depositing conductive material on an insulation layer such as a silicon oxide layer and then etching the obtained conductive material layer to form a desired metal pattern. However, by the damascene process, a groove for a desired metal pattern is formed on a underlying insulation layer and then metal is deposited to fill the groove.
Recently, a dual damascene method in which a contact hole is filled with a metal and where a metal pattern is simultaneously formed, is widely utilized. Each of U.S. Pat. Nos. 5,877,076 and 5,612,254 discloses such a dual damascene method in detail. When the metal plug and the metal pattern are simultaneously formed by the above-described method, the characteristics of the thus obtained device are improved because a uniform pattern can be obtained to an edge portion. However, a large number of processing steps are needed and the manufacturing method becomes complicated.
Accordingly, the contact hole and the metal pattern are simultaneously formed by a more simplified method. FIGS. 1A to 1D are schematic cross-sectional views which illustrate a method for manufacturing a wiring of a semiconductor device according to the conventional method.
Referring to FIG. 1A, on a semiconductor substrate 100 divided into an active region and a field region by a field oxide layer (not shown), a gate electrode 120 is formed on the active region by a conventional method. The gate electrode 120 is formed of a first conductive layer 124 constituted by a material such as conductive polysilicon doped with an impurity and a second conductive layer 126 formed from a material such as tungsten silicide or tantalum silicide. Source/drain regions 110a and 110b are formed on the active region of the semiconductor substrate 100 exposed by the gate electrode 120 by doping impurity. On the gate electrode 120, an insulating material such as BPSG (borophosphosilicate glass) is deposited by a chemical vapor deposition method to a thickness of about 3000-10000 Å in order to insulate the gate electrode 120 and a subsequently formed conductive layer.
Thereafter, CMP process is implemented to planarize the deposited insulation material, the surface of which is rough and crooked, to obtain a planarized insulation layer 130. After implementing the CMP process, a scratch 135 having a depth of 2000 Å is formed on insulation layer 130 as illustrated in FIG. 1A.
Referring to FIG. 1B, two etching processes on the insulation layer 130 are continuously carried out by utilizing photoresist patterns as etching masks to form a contact hole 140 for an electrical connection with the source or drain region 110a or 110b of a transistor with a conductive layer and to form an etching pattern 150 for the formation of a metal pattern. At this time, an upper portion of the insulation layer 130 for separating a neighboring etching pattern 150 and the contact hole 140 does not remain by the scratch 135 as shown by FIG. 1A. That is, the upper portions of the etching pattern 150 and the contact hole 140 are partially connected to form a bridge and the generation of this bridge increases as the size of a device decreases.
Referring to FIG. 1C, a barrier metal layer 155 is formed by depositing Ti/TiN on the insulation layer 130 on which the etching pattern is formed. Then, metal material such as tungsten, copper, aluminum and the like is deposited on the barrier metal layer 155 to fill the etched portion and to form a metal layer 160.
Referring to FIG. 1D, a plug 170 of the contact hole and a metal wiring 180 of the damascene shape are formed by implementing the CMP process and removing the upper portion of the insulation layer 130. At this time, the scratch formed on the insulation layer 130 is filled with metal to give a scratch pattern 175 for connecting a neighboring plug 170 of the contact hole and the metal wiring 180. This defect induces undesirable short between neighboring conductive patterns. Particularly, since the metal pattern and the plug of the contact hole are formed on the same layer, it is difficult to differentiate the plug of the contact hole from a metal pattern, and interval between metal patterns become narrower.
Thus, the formation of a bridge between the metal patterns by the scratch generated during the CMP process increases.
In order to solve this problem, various methods have been suggested. U.S. Pat. No. 5,915,175 (issued to Wise) discloses a method for solving the problem caused by the scratch. In this patent, a reflowable material such as BPSG is utilized as an insulation layer. After implementing the CMP process, the insulation layer including a scratch is reflowed and then the same insulating material is deposited to form a second insulation layer.
However, by this method, a high temperature process is required for the reflow. For example, BPSG insulation layer should be treated at about 750-1100° C. under a N2, O2 or H2O atmosphere. This complicates the manufacturing process and lowers the productivity of the device.
U.S. Pat. Nos. 5,710,460 and 5,840,503 (both issued to Leidy et al.) disclose devices having three-layered insulation layers. On an insulation layer that includes a scratch, a curable polymer such as SOG (spin-on glass) is deposited to fill the scratch. Then, heat is applied to cure the polymer and remove solvent to manufacture a polymer film. On the polymer film, an insulating material is deposited again.
However, by this method, a first heat treatment is implemented at about 100-150° C. for about 3-10 minutes and then a second heat treatment is implemented at about 350-850° C. for about 30 minutes under an inert gas atmosphere such as N2 for curing the polymer. Thus, for this method, the process is also too complicated and the productivity of the device is very low.